1. Field of the Invention
The present invention relates to a test circuit which is incorporated in a large circuit such as an LSI device to test a plurality of circuit parts forming the large circuit, and more particularly to size reduction technique of the test circuit.
2. Description of the Background Art
Recent years have seen wider use of exceedingly larger circuits such as an LSI. Designs of such circuits become more and more complex, and so do testing methods for testing such circuits. A current approach to avoid the test complexity involves division of an integrated circuit into some portions. A test circuit is inserted between the divided circuit portions. Due to this circuit design, it is possible to test each individual divided circuit portion.
FIG. 1 is a block diagram of a conventional test circuit of a scan-register system for testing circuit parts of an integrated circuit. Incorporated between the circuit parts, the test circuit carries out a test.
In a test using the test conventional circuit, test data are inputted to a selected circuit part to be tested via a parallel register which is connected to input terminals of the selected circuit part. The data are processed in the circuit part and outputted through a parallel register which is connected to output terminals of the circuit part, followed by examination of the output data. In non-test operation, data are transferred from a circuit part to a circuit part via the parallel registers so that the integrated circuit which is formed by the circuit parts performs normal operations.
In FIG. 1, the integrated circuit comprises a first circuit part 1a, a second circuit part 2a and a third circuit part 3a. The first, the second and the third circuit parts 1a, 2a and 3a have n input terminals 11, 21 and 31 and n output terminals 12, 22 and 32, respectively. The test circuit is formed by two parallel registers, one including n scan latch circuits 9.sub.1 to 9.sub.n inserted between the first circuit part 1a and the second circuit part 2a and another including n scan latch circuits 9.sub.n+1 to 9.sub.2n inserted between the second circuit part 2a and the third circuit part 3a.
The scan latch circuits 9.sub.1 to 9.sub.n each have a first input terminal a, a second input terminal b, a control terminal c, an output terminal d and another output terminal S.sub.o. Under the control of a control signal C given to the control terminal c, a signal fed to the first input terminal a is outputted at the output terminal d or a signal fed to the second input terminal b is outputted at the output terminal S.sub.o.
Next, the overall structure of the integrated circuit will be described. The input terminals a of the first to the n-th stage scan latch circuits 9.sub.1 to 9.sub.n are connected to the output terminals 12 of the first circuit part 1a. Likewise, the output terminals d are connected to the input terminals 21 of the second circuit part 2a. The output terminals S.sub.o of the scan latch circuits 9.sub.1 to 9.sub.n are connected to the second input terminals b of the scan latch circuits 9.sub.2 to 9.sub.n+1, respectively. The input terminals a of the (n+1)-th to the 2n-th stage scan latch circuits 9.sub.n+1 to 9.sub.2n are connected to the output terminals 22 of the second circuit part 2a. The output terminals S.sub.o of the (n+1)-th to the (2n-1)-th stage scan latch circuits 9.sub.n+1 to 9.sub.2n-1 are connected to the second input terminals b of the post-stage scan latch circuits 9.sub.n+2 to 9.sub.2n. The control terminals c, which are to receive the control signal C, of all of the scan latch circuits 9.sub.1 to 9.sub.2n are connected in common.
The input terminals 11 of the first circuit part 1a are connected to data input terminals I.sub.1 to I.sub.n of the integrated circuit. The third circuit part 3a has their output terminals 32 connected to data output terminals O.sub.1 to O.sub.n of the integrated circuit, respectively.
FIG. 2 is a block diagram showing an example of what structure the scan latch circuits 9.sub.1 to 9.sub.2n of FIG. 1 each have. As shown in FIG. 2, each scan latch circuit is formed by a multiplexer 7, which includes an invertor 4 and transmission gates 5 and 6, and two static latch circuits 8. In the multiplexer 7, the control signal C fed to the control terminal c is given to an input terminal of the invertor 4 and a control electrode of the transmission gate 6, a signal DI.sub.1 fed to the first input terminal a is passed to one electrode of the transmission gate 5, and a signal DI.sub.2 received at the second input terminal b is given to one electrode of the transmission gate 6. Hence, the control signal C of "L" level turns on the transmission gate 5 and turns off the transmission gate 6, passing the signal DI.sub.1 to the static latch circuits 8. On the other hand, with the control signal C of "H" level, the transmission gate 5 is unactuated and the transmission gate 6 is actuated, thereby transmitting the signal DI.sub.2 to the static latch circuits 8.
The two static latch circuits 8 form a master-slave latch circuit which operates in synchronism with a clock signal .phi.. In response to the clock signal .phi. of "H" level, data DI are allowed into the front stage static latch circuit 8 from the multiplexer 7. When the clock signal .phi. is switched to "L" level, the data DI are sent to the rear stage static latch circuit 8 and outputted therefrom while held in the front stage static latch circuit 8. In short, circuit operation of the scan latch circuits 9.sub.1 to 9.sub.2n for the "L" level control signal C is to receive the signal DI.sub.1 which is available at the first input terminals a and to output the same at the output terminals d and S.sub.o. If the control signal C has "H" level, on the other hand, the scan latch circuits 9.sub.1 to 9.sub.2n receive the signal DI.sub.2 which is available at the second input terminals b and output the same at the output terminals d and S.sub.o.
FIGS. 3A to 3D are circuit diagrams showing modifications of each static latch circuit 8. In FIGS. 3A to 3D, the symbol TG.sub.n denotes a transmission gate formed by an N type MOS transistor and the symbol TG.sub.p denotes a transmission gate formed by a P type MOS transistor. Indicated at IN1 to IN4 are invertors. The clock signal for triggering the static latch circuits 8 into operation is indicated at .phi..sub.in, while the signal inputted to the static latch circuits 8 is indicated at DI.
The static latch circuit 8 of FIG. 3A receives the data DI via one terminal of the transmission gate TG.sub.n, which also receives the control of the clock signal .phi..sub.in at its control electrode. Other terminal of the transmission gate TG.sub.n is connected to an input terminal of the invertor IN1 which has its output terminal connected to an input terminal of the invertor IN2. Hence, data DO are outputted at an output terminal of the invertor IN2. Under the control of the clock signal .phi..sub.in which is fed to the control electrode of the transmission gate TG.sub.p, the static latch circuit holds the data therein since the one electrode of the transmission gate TG.sub.p is connected to the output terminal of the invertor IN2 and other electrode of the transmission gate TG.sub.p is connected to the input terminal of the invertor IN1.
In the static latch circuit 8 of FIG. 3B, data input of the data DI is accomplished via one terminal of the transmission gate TG.sub.n, which receives the clock signal .phi..sub.in at its control electrode. Another terminal of the transmission gate TG.sub.n is connected to an input terminal of the invertor IN1 which has its output terminal connected to an input terminal of the invertor IN2. The data DO are outputted at an output terminal of the invertor IN2. In addition, the output terminal of the invertor IN1 is connected to an input terminal of the invertor IN3 and the input terminal of the invertor IN1 is connected to an output terminal of the invertor IN3, which allows that the data is held in the static latch circuit.
In the static latch circuit 8 of FIG. 3C, the clock signal .phi..sub.in is fed to the invertor IN4 where it is inverted. The reverse clock signal is then relayed to a control electrode of the first transmission gate TG.sub.p. The data DI are inputted to the transmission gate TG.sub.n, which is governed by the dock signal .phi..sub.in received at its control electrode, and to one terminal of the first transmission gate TG.sub.p, which is controlled by the reverse clock signal received at its control electrode. Other terminals of the transmission gates TG.sub.n and TG.sub.p are connected to an input terminal of the invertor IN1. An output terminal of the invertor IN1 is connected to an input terminal of the invertor IN2. The data DO are outputted at an output terminal of the invertor IN2. With the clock signal .phi..sub.in applied to the control electrode of the first transmission gate TG.sub.p and the reverse clock signal applied to the control electrode of the second transmission gate TG.sub.n, the data are held in the static latch circuit due to the structure that the transmission gates TG.sub.n and TG.sub.p have their one side electrodes connected to the output terminal of the invertor IN1 and their other side electrodes connected to the input terminal of the invertor IN1.
The static latch circuit 8 of FIG. 3D requires that the clock signal .phi..sub.in is fed to the invertor IN4 where it is inverted. The reverse clock signal is then supplied to a control electrode of the first transmission gate TG.sub.p. The data DI are inputted to the transmission gate TG.sub.n, which receives the clock signal .phi..sub.in at its control electrode, and to one terminal of the first transmission gate TG.sub.p, which receives the reverse clock signal at its control electrode. Other terminals of the transmission gates TG.sub.n and TG.sub.p are connected to an input terminal of the invertor IN1. An output terminal of the invertor IN1 is connected to an input terminal of the invertor IN2. The data DO are outputted at an output terminal of the invertor IN2. The output terminal of the invertor IN1 is connected to an input terminal of the invertor IN3 while the input terminal of the invertor IN1 is connected to an output terminal of the invertor IN3, thereby ensuring the data are held in the static latch circuit.
Operations of the test circuit will be now described. The operations are divided into two modes; that is, operation mode wherein the control signal C stays at "L" level and shifting mode wherein the control signal C stays at "H" level.
In the operation mode, all the scan latch circuits 9.sub.1 to 9.sub.2n are in a condition to receive the data which are sent to the first input terminals a. Data inputted in a parallel manner at the data input terminals I.sub.1 to I.sub.n are entered in the circuit part 1a where they are processed. The processed data are outputted at the output terminals 12. The data are thereafter advanced to the input terminals a of the scan latch circuits 9.sub.1 to 9.sub.n, latched in the first static latch circuit 8, and outputted at the output terminals d. Thus, the data outputted at the output terminals 12 are entered to the scan latch circuits 9.sub.1 to 9.sub.n, and then transmitted to the second circuit part 2a via the input terminals 21. The data are processed in the second circuit part 2a and outputted at the output terminals 22. This is followed by similar data transmission in which the data from the output terminals 22 are given to the first input terminals a of the scan latch circuits 9.sub.2n to 9.sub.n+1, latched in the first static latch circuit 8, and outputted at the output terminals d. Thus, the data outputted at the output terminals 22 are passed through the scan latch circuits 9.sub.2n to 9.sub.n+1, and thereafter transmitted to the third circuit part 3a via the input terminals 31. The data processed in the third circuit part 3a are outputted at the output terminals O.sub.1 to O.sub.n in a parallel manner. That is, in the operation mode, the circuit as a whole formed by the circuit parts 1a, 2a and 3a performs normal data processing in synchronism with the clock signal .phi..
In the shifting mode, on the other hand, all the scan latch circuits 9.sub.1 to 9.sub.2n are ready to receive the data which are given to the second input terminals b. The scan latch circuits 9.sub.1 to 9.sub.2n function as one shift register. In the first stage scan latch circuit 9.sub.1, serial data DI given to the second input terminal b are advanced to the first static latch circuit 8 and latched therein. The data are then advanced to the second static latch circuit 8 and latched therein, followed by that the data are outputted at the output terminal S.sub.o. These actions are in synchronism with the clock signal .phi.. Following this, the data are given to the second input terminal b of the second stage scan latch circuit 9.sub.2 in which they are latched in the first and the second static latch circuits 8 in sequence and then outputted at the output terminal S.sub.o in synchronism with the clock signal .phi.. By repeating this, the data are shifted by one stage in succession from the scan latch circuit 9.sub.2 to the scan latch circuit 9.sub.2n, and finally, outputted as serial data SO at the output terminal d of the last stage scan latch circuit 9.sub.2n.
Individual testing of each circuit part is accomplished by performing the operation mode operation and shifting mode operation in combination. The second circuit part 2a of FIG. 1, for example. is tested in the following manner.
First, the control signal C is switched to "H" level to bring the test circuit into the shifting mode. Next, test data DI for testing the second circuit part 2a are serially inputted, via the test data input terminals, to the second input terminal b of the first scan latch circuit 9.sub.1, thereby storing the serial data SI in the first to the n-th stage scan latch circuits 9.sub.1 to 9.sub.n.
The control signal C is switched to "L" level to enter the test circuit into the operation mode, allowing that the output data from the second circuit part 2a are entered into the (n+1)-th to the 2n-th stage scan latch circuits 9.sub.n+1 to 9.sub.2n. Following this, the test circuit is switched into the shifting mode again. The data in the scan latch circuits 9.sub.n+1 to 9.sub.2n are shifted and outputted outside the test circuit via the output terminal d of the last stage scan latch circuit 9.sub.2n. The data SO thus outputted are then examined.
As can be seen from the foregoing, the conventional test circuit, the structure of which is as heretofore described, requires a large circuit area compared to circuit parts which perform normal circuit operations.